1. Field of the Invention
The present invention relates to a semiconductor memory device having a spare memory array for repairing a defective memory cell and to a method of testing the memory device.
2. Description of the Related Art
FIG. 33 schematically shows an arrangement of a main portion of a conventional semiconductor memory device such as a dynamic type random access memory.
Referring to FIG. 33, the memory device includes four memory arrays MA1-MA4 each having a plurality of memory cells arranged in rows and columns, row decoders RD1-RD4 provided corresponding to the respective memory arrays MA1-MA4, spare memory arrays SMA1-SMA4 provided corresponding to the respective memory arrays MA1-MA4, spare row decoders SR1-SRD4 provided corresponding to the respective spare memory arrays SMA1-SMA4, and a column decoder CD provided in common to the memory arrays MA1-MA4 and to the spare memory arrays SMA1-SMA4.
Each of memory arrays MA1-MA4 includes 16 word lines WL(m, 1)-WL(m, 16) each connecting a row of memory cells, where m is one of integers 1-4.
Row decoder RDm selects a word line WL(m, n) in a corresponding memory array MAm in accordance with a row address signal and an array address signal with n=1-16. The row address signal designates a row or a word line in each of memory arrays MA1-MA4, and the array address signal designates a memory array.
Each of spare memory arrays SMA1-SMA4 includes four word lines SWL(m, 1)-SWL(m, 4) and can repair at most four defective word lines in corresponding memory arrays MA1-MA4.
Each of spare row decoders SRD1-SRD4 has a failure address designating a defective word line in a corresponding memory array programmed therein, and when a defective word line is addressed, a spare row decoder having a corresponding failure address programmed therein selects a corresponding spare word line in the corresponding spare memory array.
The column decoder CD selects a column in each of memory arrays MA1-MA4 and spare memory arrays SMA1-SMA4 in accordance with a column address signal.
In the arrangement of FIG. 33, repairing of a defective word line is effected in the following manner. If a word line WL(1, 3) in memory array MA1 is found defective, the word line WL(1, 3) is replaced by a spare word line SWL(1, 1) in spare memory array SMA1. The spare memory array SMA1 can repair a defective word line WL(1, n) (n=1-16) only in memory array MA1, and cannot repair a defective word line in any other memory arrays MA2-MA4.
In FIG. 33, it is shown, as an example, that a word line WL(1, 3) is replaced by a spare word line SWL(1, 1), a word line WL (1, 6) is replaced by a spare word line SWL(1, 2), a word line WL(1, 12) is replaced by a spare word line SWL(1, 3) and a word line WL(1, 16) is replaced by a spare word line SWL(1, 4).
FIG. 34 shows a schematic arrangement for replacement control circuitry used in the memory device shown in FIG. 33. Referring to FIG. 34, four program circuits PR1-PR4 are provided for storing defective word line address signals and for determining whether a defective word line is addressed. Each of program circuits PR1-PR4 stores defective word line addresses repaired by the spare word lines at the same locations in the respective spare memory arrays SMA1-SMA4. That is, program circuit PR1 stores the addresses of defective word lines replaced by the spare word line SWL(1, 1), SWL(2, 1), SWL(3, 1) and SWL(4, 1). Thus, program circuit PR1 includes four link circuits LINK1-LINK4 for storing the defective word line addresses repaired by the spare word lines SWL(1, 1), SWL(2, 1), SWL(3, 1) and SWL(4, 1), respectively. Program circuit PR4 similarly includes four link circuits LINK1-LINK4 for storing defective word line addresses repaired by the spare word lines SWL(1, 4), SWL(2, 4), SWL(3, 4) and SWL(4, 4), respectively.
Decision circuits D1-D4 are provided corresponding to the program circuits PR1-PR4. Decision circuits D1-D4 each decide whether a corresponding group of spare word lines is designated in response to the outputs of program circuits PR1-PR4 and generate a control signal SEEx(x=1-4) based on the result of determination.
Spare row decoders SRD(1, 1), SRD(2, 1), SRD(3, 1) and SRD(4, 1) receive the control signal SEE1 from the decision circuit D1. In general, spare row decoder SRD(m, x) receives an array designating signal BSm and a control signal SEEx, where x=1-4, m=1-4.
Each of row decoders RD(m, n) is provided with a gate Gmn for enabling and disabling a corresponding row decoder RD(m, n) in accordance with the array designating signal BSm and the control signal SEEx. In FIG. 34, only the gates G11, G21, G31 and G41 provided for row decoders RD(1, 1), RD(2, 1), RD(3, 1) and RD(4, 1) are representatively shown. Thus, row decoders RD(m, 1)-RD(m, 16) are grouped according to the control signals SEE1-SEE4.
A gate Gmn supplies an array request signal BSDmn in response to the signals BSm and SEEx to a row decoder RD(m, n).
FIG. 35 specifically shows the configuration of circuitry of FIG. 34. In FIG. 35, a spare row decoder SRD(m, x), a row decoder RD(m, n), a program circuit PRx, and related circuitry are representatively shown.
Program circuit PRx includes link circuits LINK1-LINK4 of the same configuration. The link circuit LINK1 includes a p channel MOS transistor QP11 responsive to a precharge signal PR for precharging a node N1 to a high voltage VPP, fuse elements F1.1-F1.8 connected to the node N1 in parallel with each other, and n channel MOS transistors QN1.1-QN1.8 connected respectively between the fuse elements F1.1-F1.8 and a ground potential node. MOS transistors QN1.1-QN1.8 receive internal (predecoded) address signals Xi(i=1-4) and Xj(j=5-8) at their gates. Upon programming a defective word line address, link elements F1.1-F1.8 are selectively cut off or blown off. More specifically, fuse elements among fuse elements F1.1-F1.8 corresponding to a defective word line address are cut off.
Decision circuit Dx includes a NOR gate NO31 receiving outputs of link circuit LINK1-LINK4, and an inverter INV31 for inverting an output of NOR gate NO31 to generate control signal SEEx.
A spare row decoder SRD(m, x) provided for a spare word line SWL(m, x) includes a NAND gate NA31 receiving the control signal SEEx and an array designating signal BSm to generate a spare word line designating signal SWEm.x, and an inverter INVSm.x for inverting the output SWEm.x of NAND gate NA31 to generate a spare word line drive signal at a high voltage VPP level onto the spare word line SWL(m, x). Here, the circuitry shown in FIG. 35 operates on the high voltage VPP, or employs the high voltage VPP as an operating power supply voltage.
A gate Gmn provided for the row decoder RD(m, n) includes an inverter INV32 for inverting the array designating signal BSm, a NOR gate NO32 receiving an output of inverter 32 and the control signal SEEx to generate a decoder enabling signal BSDmn.
A row decoder RD(m, n) includes a three-input NAND gate NAm.n receiving the signal BSDmn and internal (predecoded) address signal Xi and Xj, and an inverter INVm.n for inverting an output of NAND gate NAm.n to generate a word line drive signal at a high voltage level onto a word line WL(m, n). Now, operation of the circuitry of FIG. 35 will be briefly described.
In a precharge (standby) state, the precharge signal PR is at a low level to turn on MOS transistor QP1.1 in link circuit LINK1. Node N1 is precharged to a high level of the high voltage VPP. Link elements F1.1-F1.8 are previously programmed.
In an active state, the precharge signal PR goes high to turn off MOS transistor QP1.1. When a defective word line is addressed, as corresponding fuse elements are cut off, the node N1 maintains the high level at high voltage VPP. When a word line address not programmed in the link circuit LINK1 is supplied, at least one of MOS transistors QN1.1-QN1.8 turns on to discharge the node N1 to a ground potential.
Thus, the decision circuit Dx generates a high level control signal SEEx when an addressed word line should be replaced by one of spare word lines SWL(m, x) (m=1-4). Otherwise, the control signal SEEx maintains a low level.
When the control signal SEEx and the array designating signal BSm both go high, the spare row decoder SRD(m, x) supplies a high level spare word line drive signal at VPP level onto the spare word line SWL(m, x). Otherwise, the spare row decoder SRD(m, x) supplies a low level signal.
When the control signal SEEx is at a high level, NOR gate NO32 in the gate Gmn supplies a low level signal BSDmn to disable the row decoder RD(m, n).
When the control signal SEEx is at a low level, NOR gate NO32 is enabled, and the gate Gmn passes the array designating signal BSm therethrough. If the signals BSm, Xi and Xj designate the word line WL(m, n), row decoder RD(m, n) supplies a high level word line drive signal onto the word line WL(m, n).
FIG. 36 shows the arrangement for the row decoders and the spare row decoders for the memory array MA1. Referring to FIG. 36, row decoder RD1 includes row decoders RD(1, 1), R(1, 2) each including a NAND gate NA(1, n) and an inverter INV1.n. NAND gates NA(1, 1), NA(1, 2) receive different combinations of the signals Xi and Xj. The decoder enable signals BSD1n (n=1-16) are divided into groups according to the control signals SEEx.
For spare decoder SRD1, only inverters INVS1.1 and INVS1.4 are representatively shown.
FIG. 37 shows an arrangement related to a column in a memory cell array. Referring to FIG. 37, a column includes a pair of bit lines BL and /BL connecting a column of memory cells MC. In FIG. 37, a memory cell MC provided corresponding to a crossing of the bit line BL and a word line WL(m, n) is representatively shown. Memory cell MC includes a capacitor CS for storing data in a form of electric charges, and a transfer gate QN31 responsive to a potential on word line WL(m, n) for coupling the capacitor CS and the bit line BL. The capacitor CS receives a cell plate voltage VCP at an intermediate potential (=Vcc/2).
A pair of bit lines BL and /BL is provided with a sense amplifier SA for differentially amplifying the potentials on bit lines BL and /BL, and a precharge/equalize circuit BLEQ responsive to a precharge/equalize signal EQ for precharging and equalizing the bit lines BL and /BL to an intermediate voltage VBL(=Vcc/2).
The sense amplifier SA includes cross-coupled MOS transistors of a flipflop type.
Precharge/equalize circuit BLEQ includes an n channel MOS transistor QN32 for electrically connecting the bit lines BL and /BL, an n channel MOS transistor QN33 for transferring the intermediate voltage to the bit line BL, and an n channel MOS transistor QN34 for transferring the intermediate voltage VBL to the bit line /BL. MOS transistors QN32-QN34 turn on when the signal EQ goes high to indicate a standby state.
In operation, the signal EQ is at a low level, and MOS transistors QN32-QN34 are turned off. The bit lines BL and /BL are brought into an electrically floating state at the intermediate voltage VBL. When the word line WL(m, n) is selected, the potential thereof goes high to turn on the transfer gate QN31. Thus, the potential of bit line BL changes according to the data stored in the capacitor CS. The bit line /BL maintains the intermediate voltage VBL level. Then, the sense amplifier SA is activated to differentially amplifying the potentials on the bit lines BL and /BL.
According to an output of a column decoder (CD), the pair of bit lines BL and /BL is selected, and data writing or reading is performed to the memory cell MC.
After completion of memory cycle, the word line WL (m, n) potential goes low, and the transfer gate QN31 turns off. The sense amplifier SA is deactivated, and the signal EQ goes high. MOS transistors QN32-QN34 turn on to precharge and equalize the bit lines BL and /BL to the intermediate voltage VBL.
Since the word line WL(m, n) is raised to the high voltage VPP higher than an operating power supply voltage VCC, voltage at VCC level can be written into the memory cell capacitor CS without a loss due to the threshold voltage of transfer gate QN31. In addition, the transfer gate QN31 can be turned on quickly.
Using the redundant scheme as described above, a word line WL(m, n) can be repaired even if the memory cell MC is defective, or the word line WL(m, n) is open-circuited.
However, if word line WL(m, n) and the bit line BL is short-circuited as shown in FIG. 38 at R1, a current flows to the word line WL(m, n) from the bit line BL in a standby state. The word line WL(m, n) potential is discharged to a ground potential through a word driver (an inverter in a corresponding row decoder). Thus, the intermediate voltage VBL lowers, and in addition the standby current Icc2 is increased.
If the word line WL(m, n) is short-circuited with the cell plate voltage VCP supply line as shown in FIG. 38 at R2, the consumed current is increased and the cell plate voltage VCP is also lowered.
If the intermediate voltage VBL supply line is short-circuited with the bit line BL or /BL as shown at R3a or R3b in FIG. 38, the potential at bit line BL or /BL is not fully and correctly amplified by sense amplifier SA, and current flows into or out of the bit line BL or /BL to increase the current consumption in memory operation.
In addition, if sense amplifier SA is short-circuited with a VCC supply line or a ground line, a leakage current is caused. This holds for a defective word driver.
Such short-circuiting failure cannot be repaired by the conventional word line replacement scheme, because the short-circuit failure exists in a memory array.
In order to repair such short-circuit failure, an array-by-array replacement as shown in FIG. 39 is proposed by Kitsukawa et al., in "DRAM Technologies for File Application", 1993 IEEE ISSCC, Digest of Technical Papers, Feb. 24, 1993, pp. 48 and 49.
Referring to FIG. 39, a memory device includes four memory arrays MA1-MA4 having memory cells arranged in rows and columns, and a spare memory array SMA having the same size as each of memory arrays MA1-MA4. Memory arrays MA1-MA4 are provided with row decoders RD1-RD4, respectively, and the spare memory array SMA is provided with a spare row decoder SRD. A column decoder CD is provided in common for the arrays MA1-MA4 and SMA.
Row decoders RD1-RD4 receive the high voltage VPP on the source line 1a through fuse elements F41-F44, respectively, and the spare row decoder SRD receives the high voltage VPP through a switching element SW3.
Memory arrays MA1-MA4 receive the voltage VBL (VCP) on the supply line 1b through fuse elements F31 through F34, and the spare memory array SMA receives the voltage VBL (VCP) through a switching element SW2.
If a failure which could not be repaired by replacement of a word line is found in the memory array MA1, the fuse elements F31 and F41 are blown off, and the switching elements SW2 and SW3 are made turned on. In addition, an array address is programmed such that the spare memory array SMA is accessed when the memory array MA1 is accessed.
Kitsukawa describes that a word line replacement scheme will not sufficiently increase the product yield as the memory capacity increases, and that such block redundancy for array replacement would not significantly increase the chip area penalty because the number of memory arrays (blocks) is increased and array block size is reduced as the memory capacity increases.
However, according to such block redundancy scheme, even when only a failure which can be repaired by a word line replacement is present, a memory array is replaced with the spare memory array. If defective word lines are dispersed over memory arrays due to small size particles which tends to disperse over memory arrays, such defective word lines are not repaired even if the number of defective word lines is smaller than that of word lines in the spare memory array.
In addition, such block redundancy scheme does not allow the standby current test on an array basis and requires a long time for detecting a defective array.
Thus, in order to increase the product yield, it would be required that the word line by word line replacement and the array by array replacement both can be supported in a semiconductor memory device.
However, if the conventional word line replacement scheme and the conventional block redundancy scheme both are supported in a semiconductor memory device, chip area penalty is increased, the number of fuse elements is increased, and replacement control circuitry become complicate and large in size.